High-voltage output circuit for a driving circuit of a plasma

ABSTRACT

A high-voltage output circuits according to the present invention comprise a high-voltage level shifter and a high-voltage output means including a high-voltage NMOS as a pull-up element, or a bootstrapping circuit, wherein the same input voltage as a predetermined output voltage and a data signal are inputted and an output voltage of a high-voltage pulse corresponding to the data signal is outputted, and which can prevent a drop in a threshold voltage of the high-voltage element with using high-voltage NMOS transistors only and therefore can reduce an area as compared with a structure using high-voltage PMOS transistors for a full swing.

TECHNICAL FIELD

[0001] The present invention relates to a high-voltage output circuitfor a driving circuit of a plasma display panel and the like. Moreparticularly, the present invention relates to a high-voltage outputcircuit for a driving circuit of a plasma display panel which comprisesa high-voltage level shifter and a high-voltage output means including ahigh-voltage NMOS as a pull-up element, wherein the same input voltageas a predetermined output voltage and a data signal are inputted and anoutput voltage of a high-voltage pulse corresponding to the data signalis outputted, and which can prevent a drop in a threshold voltage of thehigh-voltage element with using high-voltage NMOS transistors only andtherefore can reduce an area as compared with a structure usinghigh-voltage PMOS transistors for a full swing.

BACKGROUND ART

[0002]FIG. 1 shows a control circuit block 100 in a conventional plasmadisplay panel as a detailed block diagram. In FIG. 1, a clock signal, adata signal, and horizontal and vertical synchronizing signals areinputted to the control circuit block 100. A pulse of an aftermentionedwaveform is applied to each address electrode 32 by means of a displaydata controller 105 and an address driver 101, and a pulse of anaftermentioned waveform is applied to each Y electrode 14 from an Ycommon driver 104 by means of a scan driver controller 107, a commondriver controller 108 and an Y common driver 104 of a panel drivingcontroller 106. Further, a pulse of an aftermentioned waveform by meansof the common driver controller 108 and an X common driver 103.

[0003] There are a selective write address method and a selective eraseaddress method in the driving method of the plasma display panel. In theselective write address method, electric charges are formed only fordisplay cells 36 a to be turned on in an address discharge period aftermaking electric charge in all discharge cells zero in a reset period.Then, sustain discharges are carried out. In the selective erase addressmethod, uniform charges are formed for all display cells 36 a in thereset period and then is erased only for display cells 36 a to be turnedoff in an address discharge period. Subsequently, sustain discharges arecarried out for the rest cells.

[0004]FIG. 2 illustrates a waveform for driving the conventional plasmadisplay panel in a selective write address method. In FIG. 2, all Yelectrodes become a level of 0 V during a reset period of each subfield,and at the same time a full writing pulse of a high-voltage(about 350 V)is applied to each X electrode. Then, discharge is executed for alldisplay cells of all display lines despite of display states up to thattime. At this time, an electric potential of an address electrode isabout 100 V. By this full write discharge, wall charges are accumulatedon a front dielectric layer covering the X electrodes and the Yelectrodes. That is, minus wall charges are accumulated on the Xelectrodes and plus wall charges on the Y electrodes. Then, by makingthe potential of the X electrodes and the address electrodes 0 V, thevoltage of wall charges themselves at all display cells becomes over adischarge starting voltage, thereby causing a discharge, which becomesself-neutralized and finished. That is called a self-erase discharge. Bythis self-erase discharge, the states of all display cells in the panelbecome uniform without any wall charge, thereby becoming states in whichthe subsequent address(write) discharge can be stably executed. And, asshown in FIG. 2, selectively and slowly increasing priming erase pulsescan be applied to the Y electrodes. All display cells are completelyinitialized by additionally discharging cells, in which wall charges arenot completely extinguished, using these priming erase pulses.

[0005] Next, in the address period, address discharge is executed inorder to turn on or off the display cells according to the display data.First, a predetermind voltage(about 50 V) is applied to each X electrodeand scan pulses(about −150 V) are applied to the Y electrodes in order.At the same time, address pulses(about 50 V) are selectively applied tothe address electrodes corresponding to display cells to be turned onamong the address electrodes, that is display cells where sustaindischarges are carried out, thereby causing discharge between eachaddress electrode for the display cells to be turned on and each Yelectrode and accumulating quantity of wall charges to enable subsequentsustain discharges. And, a predetermined voltage(about −50V) is appliedto the Y electrodes to which scan pulses are not applied so as not tocause any sustain discharge.

[0006] Then, in the sustain discharge period, a sustain discharge pulseis alternatively applied to each Y electrode and each X electrode andthe sustain discharge is performed, thereby displaying a picture of onesubfield. That is, discharges occur in the display cells which wallcharges are accumulated on during the address discharge period, whensustain discharge pulses are overlapped to the wall charges, while adischarge does not occur in the display cells which wall charges are notaccumulated on during the address discharge period, although sustaindischarge pulses are applied. Thus, a picture of one subfield can becomedisplayed. And, in order to avoid a discharge between the addresselectrodes and the X electrodes or Y electrodes, a predeterminedvoltage(about 65V) is applied to the address electrodes.

[0007]FIG. 3 illustrates a circuit diagram of a high-voltage outputterminal circuit of a conventional integrated circuit for driving theplasma display panel. In FIG. 3, the high-voltage output terminalcircuit comprises a high-voltage level shifter to convert a logicvoltage of the circuit into a high-voltage level of a desirable drivingvoltage, and a high-voltage output means to receive the voltage of thehigh-voltage level shifter as an input and to output it after buffering.

[0008] The high-voltage level shifter comprises a LVPMOS1 and a LVPMOS2of low voltage PMOS transistors to function as a latch, a LVNMOS1 and aLVNMOS2 of low voltage NMOS transistors as an input part which a lowlevel voltage is applied to, and a HVPMOS1 and a HVPMOS2 of high voltagePMOS transistors to protect the LVNMOS1 and the LVNMOS2 as the inputpart. The high-voltage output means comprises a HVPMOS3 of a highvoltage PMOS transistor, and a HVNMOS1, a HVNMOS2 and a HVNMOS3 of highvoltage NMOS transistors.

[0009] When a data signal of 0V as a low signal is applied, the LVNMOS1becomes turned off, and the LVNMOS2 on since a high signal of 5V isapplied after passing through an inverter. Then, a voltage V_(H) isapplied to a node 1 and a voltage (V_(H)−V_(Z)) is applied to a node 2,wherein V_(Z) is a voltage of a Zener diode which is commonly 5V. As aresult, the HVPMOS3 becomes turned on and a voltage V_(H) is applied toa node 3. At this time, 0V of a low signal is applied to the HVNMOS1 andthe HVNMOS3 of the high-voltage output means, which are kept in an OFFstate, and a voltage V_(H) is applied to a gate part of the HVNMOS2.Thus, a voltage (V_(H)−V_(THN)) dropped by a threshold voltage V_(THN)of a high-voltage NMOS transistor from an input voltage V_(H) of ahigh-voltage is outputted as a final output voltage HV_(out) Forexample, when V_(H) is 180V and the threshold voltage V_(THN) of ahigh-voltage NMOS transistor is 2V, 178V becomes outputted. When thedata signal becomes 5V of a high signal, 0V becomes outputted contraryto the above. That is, a PMOS is around two times bigger in size than anNMOS in size of a device for providing hundreds of milliampere incurrent where a high-voltage PMOS device is adopted as a pull-up deviceof a high-voltage output terminal so that an input voltage V_(H) of ahigh-voltage to an IC chip becomes an output voltage HV_(out).Therefore, there is one problem that size of the IC chip becomes biggerthan in case of an employment of a high-voltage NMOS as the pull-updevice. Also, where a high-voltage NMOS is employed as the pull-updevice in order to reduce size, it is disadvantageous that a voltage(V_(H)−V_(THN)) dropped by a threshold voltage V_(THN) of a high-voltageNMOS transistor from an input voltage V_(H) of a high-voltage isoutputted as an output voltage HV_(out).

DISCLOSURE OF INVENTION

[0010] Accordingly, the present invention is made in order to solve theabove problems, and one object of the present invention is to provide ahigh-voltage output circuit for a driving circuit of a plasma displaypanel which comprises a high-voltage level shifter and a high-voltageoutput means including a high-voltage NMOS as a pull-up element, whereinthe same input voltage as a predetermined output voltage and a datasignal are inputted and an output voltage of a high-voltage pulsecorresponding to the data signal is outputted, and which can prevent adrop in a threshold voltage of the high-voltage element with usinghigh-voltage NMOS transistors only and therefore can reduce an area ascompared with a structure using high-voltage PMOS transistors for a fullswing.

[0011] To accomplish the object of this invention, a high-voltage outputcircuit for a driving circuit of a plasma display panel is provided inaccordance with one embodiment of the invention, which comprises ahigh-voltage level shifter and a high-voltage output means including ahigh-voltage NMOS as a pull-up element, wherein the same input voltageas a predetermined output voltage and a data signal are inputted and anoutput voltage of a high-voltage pulse corresponding to the data signalis outputted, said high-voltage output circuit being characterized byfurther comprising: a boosting voltage generator between the inputvoltage and the high-voltage level shifter for raising the input voltageto a higher voltage by a threshold voltage of a high-voltage NMOStransistor so as to prevent a voltage drop in the output voltage of thehigh-voltage NMOS of the high-voltage output means.

[0012] Said high-voltage level shifter comprising: a LVPMOS1 and aLVPMOS2 transistors for constituting a latch; a HVPMOS1 and a HVPMOS2transistors for clamping a gate voltage of, and protecting, the LVPMOS1and the LVPMOS2 transistors; a LVNMOS1 and a LVNMOS2 transistors forturning on/off the LVPMOS1 transistor and turning off/on the LVPMOS2transistor by means of the HVPMOS1 and the HVPMOS2 transistors bybecoming off and on/on and off by means of a low signal/a high signal ofthe data line, respectively; a HVNMOS1 and a HVPMOS3 transistors tobecome off/on and on/off by means of the low signal/the high signal ofthe data line, respectively, so as to apply a voltage to a gate of thehigh-voltage NMOS transistor of the high-voltage output means from saidHVPMOS3 transistor when the data line is a low signal.

[0013] Furthermore, the present invention is to provide a high-voltageoutput circuit for a driving circuit of a plasma display panel, inaccordance with another embodiment of the invention, which comprises ahigh-voltage level shifter and a high-voltage output means including ahigh-voltage NMOS transistor as a pull-up element, wherein the sameinput voltage as a predetermined output voltage and a data signal areinputted and an output voltage of a high-voltage pulse corresponding tothe data signal is outputted, said high-voltage output circuit beingcharacterized by further comprising: a bootstrapping high-voltage levelshifter between the high-voltage level shifter and the high-voltageoutput means for raising the input voltage to a higher voltage by athreshold voltage of a high-voltage NMOS transistor so as to prevent avoltage drop in the output voltage of the high-voltage NMOS of thehigh-voltage output means. The bootstrapping high-voltage level shiftershown in FIG. 7 comprises a charge pumping means having a buffer and acapacitor for the bootstrapping, thereby applying a higher voltage bythe threshold voltage than the final output voltage to a gate part ofthe high-voltage NMOS transistor or the pull-up element of thehigh-voltage output means and being capable of outputting the inputvoltage without dropping the threshold voltage on outputting thehigh-voltage. The high-voltage level shifter comprises a LVP1 and a LVP2transistors for constituting a latch; a HVP1 and a HVP2 transistors forclamping a gate voltage of, and protecting, the LVP1 and the LVP2transistors; a LVN1 and a LVN2 transistors for turning on/off the LVP1transistor and turning off/on the LVP2 transistor by means of the HVP1and the HVP2 transistors by becoming off and on/on and off by means of alow signal/a high signal of the data line, respectively; a HVN1 and aHVP3 transistors to become off/on and on/off by means of the lowsignal/the high signal of the data line, respectively, so as to apply avoltage to a gate of the high-voltage NMOS transistor of thehigh-voltage output means 120 from said HVP3 transistor when the dataline is a low signal.

[0014] The high-voltage output circuits of such constructions can beincluded by a scan driving IC and a data driving IC as a driving IC of aplasma display panel and by a scan driving IC and a data driving IC as adriving IC of a flat display.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a detailed block diagram showing a control circuit and adriving part in a conventional plasma display panel.

[0016]FIG. 2 is a waveform for driving the conventional plasma displaypanel in a selective write address method.

[0017]FIG. 3 illustrates a circuit diagram of a high-voltage outputterminal circuit of a conventional integrated circuit for driving theplasma display panel.

[0018]FIG. 4 is a block diagram of a high-voltage output terminalcircuit of an integrated circuit for driving the plasma display panelaccording to one embodiment of the present invention.

[0019]FIG. 5 is a detailed circuit diagram of FIG. 4.

[0020]FIG. 6 is a block diagram of a high-voltage output terminalcircuit of an integrated circuit for driving the plasma display panelaccording to another embodiment of the present invention.

[0021]FIG. 7 is a detailed circuit diagram of FIG. 6.

[0022]FIGS. 8a to 8 c illustrate waveforms at nodes 2 and 3 forcomparing an output voltage in the conventional high-voltage outputterminal circuit with an output voltage in the high-voltage outputterminal circuit according to the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0023] Now, a preferred embodiment of the present invention will bedescribed in detail with reference to the accompanying drawings.

[0024] a high-voltage output terminal circuit of an integrated circuitfor driving the plasma display panel according to one embodiment of thepresent invention is illustrated as an block diagram in FIG. 4.

[0025] In FIG. 4, the high-voltage output terminal circuit of anintegrated circuit for driving the plasma display panel and the likeaccording to one embodiment of the present invention, as described withreference to the prior art, which can be employed as an output terminalof a driving IC to be used in a circuit for driving the plasma displaypanel, performs a function of converting an interior logic voltage levelof the driving IC into a high-voltage level.

[0026] The high-voltage output terminal circuit comprises a high-voltagelevel shifter 10 for converting a logic voltage of the circuit into ahigh-voltage level of a desirable driving voltage V_(H) for a plasmadisplay panel, and a high-voltage output means 20 for receiving thevoltage of the high-voltage level shifter 10 as an input and outputtinga high-voltage, the high-voltage output means 20 performing a push-pullaction. That is, where high-voltage PMOS devices are used as a pull-updevice of a high-voltage output terminal, an input high-voltage V_(H) toa chip becomes an output voltage HV_(out). However, in size of a devicecapable of supplying hundreds of milliampere in current, a PMOStransistor is around two times the size of an NMOS transistor, andtherefore in size of IC, one using high-voltage PMOS transistors becomesbigger than that using high-voltage NMOS transistors. Meanwhile, wherehigh-voltage PMOS transistors are used as a pull-up device of ahigh-voltage output terminal, it is advantageous that the size can bereduced, but, disadvantageously, since an input voltage V_(H) of anhigh-voltage is dropped by a threshold voltage V_(THN) of anhigh-voltage NMOS transistor, the dropped voltage (V_(H)−V_(THN)) isoutputted as an output voltage HV_(out).

[0027] Therefore, in the present invention, a high-voltage outputterminal circuit of a driving IC in a plasma display panel is providedwhich the same voltage V_(H) as the input high-voltage V_(H) can becomethe output voltage HV_(out) with using high-voltage NMOS transistors asthe pull-up device of the high-voltage output terminal

[0028] That is, in FIG. 4, in order to prevent the drop of the outputvoltage HV_(out), the present invention is characterized in that aboosting voltage generator 30 is provided between the input voltageV_(H) and the high-voltage level shifter 10, which can raise the inputvoltage V_(H) to a higher voltage (V_(H)+V_(THN)) by a threshold voltageV_(THN) of a high-voltage NMOS transistor and apply the higher voltage(V_(H)+V_(THN)) to the high-voltage level shifter 10. Any boostingvoltage generator 30 can be adopted if it can raise a voltage by thethreshold voltage V_(THN) however it may be constituted according to theprior art.

[0029] In FIG. 4, the present invention comprises the boosting voltagegenerator 30, the high-voltage level shifter 10 for converting a logicvoltage into a high-voltage level of a desirable driving voltage for aplasma display panel, and an HVNMOS2 and an HVNMOS3 transistors as thehigh-voltage output means 20 for receiving the voltage of thehigh-voltage level shifter 10 as an input and outputting a high-voltageafter buffering. The boosting voltage generator 30 receives a voltageV_(H) as an input voltage and generates a voltage V_(PP)(V_(H)+V_(THN)).Therefore, a switching voltage at the gate part of the HVNMOS2 has arange of 0V to a voltage (V_(H)+V_(THN)), said switching voltage beingthe output voltage of the high-voltage level shifter 10. As a result,the final output voltage HV_(out) performs a switching action of avoltage 0 to a voltage V_(H), thereby performing a full swing action.

[0030]FIG. 5 illustrates a detailed circuit diagram of FIG. 4. Theoperation is briefly described as follows. In FIG. 5, the same voltageas an output voltage is applied to a terminal V_(H), and the outputvoltage (V_(H)+V_(THN)) of the boosting voltage generator 30 is appliedto a terminal V_(PP) of the high-voltage level shifter 10. A voltage(V_(PP)−V_(Z)) of a reference voltage generator is applied to a terminalV_(REF). A LVPMOS1 and a LVPMOS2 are low-voltage PMOS devices, and anHVPMOS1, an HVPMOS2 and an HVPMOS3 are high-voltage PMOS devices. Also,a LVNMOS1 and a LVNMOS2 are low-voltage NMOS devices, and a HVNMOS2 anda NVNMOS3 of an output terminal are high-voltage NMOS devices. Alldiodes used in here are Zenor diodes. The Zenor diodes D1 and D2 areturned on when a voltage between a gate and a source of the LVPMOS1 orthe LVPMOS2 used as a latch is dropped above 5V, thereby performing afunction of protecting the devices. A function of the HVPMOS1 and theHVPMOS2 is to protect the LVPMOS1 and the LVPMOS2 by clamping each gatevoltage of the LVPMOS1 and the LVPMOS2. When a low signal of a data lineData becomes 0V, the LVNMOS1 becomes an OFF state and the LVNMOS2passing an inverter becomes an ON state. As a result, the LVPMOS1 of thelatch becomes an ON state and the LVPMOS2 becomes an OFF state. Thus, avoltage of a node 2 becomes a voltage (V_(PP)−V_(Z)(5V)), the HVPMOS3becomes an ON state, and a voltage of a node 3 will be a voltage V_(PP).In this case, since the HVMOS1 and the HVNMOS3 become an OFF state, theHVNMOS2 is kept in an ON state, and the HVNMOS3 is kept in an OFF state,a high-voltage is outputted from the output voltage terminal HV_(out).Since a voltage V_(PP)(V_(H)+V_(THN)) is applied to a gate of theHVNMOS2, an output level of the high-voltage in the output voltageterminal HV_(out), becomes a voltage V_(H), which is not dropped by athreshold voltage V_(THN) of the HVNMOS2, the voltage V_(H) becomingoutputted.

[0031] Meanwhile, if a high signal is applied to the data line Data, itoperates to the contrary and a voltage 0V becomes outputted in theoutput voltage terminal HV_(out).

[0032] Therefore, in the present invention, an input voltage V_(H) of ahigh-voltage applied can be outputted in itself with using ahigh-voltage NMOS as a pull-up element of a high-voltage output terminaland without dropping a voltage by a threshold voltage of thehigh-voltage element.

[0033]FIG. 6 illustrates a block diagram of a high-voltage outputterminal circuit of an integrated circuit for driving the plasma displaypanel and the like according to another embodiment of the presentinvention. The high-voltage output terminal circuit, as one method of abootstrapping level shifter, comprises a high-voltage level shifter 110which is described in the above background art, a bootstrappinghigh-voltage level shifter 130 using an aftermentioned charge pumpingmeans Cpump, and a high-voltage output means 120 including a HVN2 and aHVN3 of a high-voltage output terminal and for receiving the voltage ofthe high-voltage level shifter 10 as an input and outputting ahigh-voltage after buffering. In such a construction, a voltage isbootstrapped by a threshold voltage V_(THN) of the HVN2 in thebootstrapping high-voltage level shifter 130. A switching voltage at agate part of the HVN2 as an output voltage of the bootstrappinghigh-voltage level shifter 130 has a range of 0V to a voltage(V_(H)+V_(THN)). As a result, the final output voltage HV_(out) performsa switching action of a voltage 0 to a voltage V_(H), thereby performinga full swing action.

[0034]FIG. 7 illustrates a detailed circuit diagram of the high-voltageoutput terminal circuit for driving the plasma display panel. Theoperation is as follows. An output voltage is applied to a terminalV_(H), and a voltage (V_(H)−V_(Z)) is applied to a terminal V_(REF) froma reference voltage generator. A LVP1 and a LVP2 are low-voltage PMOSdevices, and an HVP1, an HVP2 and an HVP3 are high-voltage PMOS devices.Also, a LVN1 and a LVN2 are low-voltage NMOS devices, and a HVN2 and aNVN3 of an output terminal are high-voltage NMOS devices. All diodesused in here are Zenor diodes. The Zenor diodes D1 and D2 are turned onwhen a voltage between a gate and a source of the LVP1 or the LVP2 usedas a latch is dropped above 5V, thereby performing a function ofprotecting the devices. A function of the HVP1 and the HVP2 is toprotect the LVP1 and the LVP2 by clamping each gate voltage of the LVP1and the LVP2. When a low signal of a data line Data becomes 0V, the LVN1becomes an OFF state and the LVN2 passing an inverter becomes an ONstate. As a result, the LVP1 of the latch becomes an ON state and theLVP2 becomes an OFF state. Thus, a voltage of a node 2 becomes a voltage(V_(H)−V_(Z)(5V)) and the HVPMOS3 becomes an ON state. In this time, avoltage of a node 3 will be kept in a voltage (V_(H)−V_(THN)) dropped bya threshold voltage V_(THN) of the HVN2, and a predetermined constantquantity of charges are supplied from the charge pumping means Cpump,being bootstrapped by a voltage ΔV_(B). Therefore, a voltage in the node3 becomes a voltage (V_(H)−V_(THN)+ΔV_(B)). Here, ΔV_(B) can be obtainedfrom the equation of ΔV_(B)=V_(Z)·C_(B)/(C_(B)+C_(IN)).

[0035] Here, C_(B) is a capacitor of the charge pumping means Cpump,C_(IN) is an input capatance of a HVP3, and V_(Z) is a voltage betweenopposite terminals of the Zener diode. In an actual design, ΔV_(B) wasset into a voltage of 2V_(THN). In this case, the HVN1 and the HVN3become an OFF state and the HVN2 is kept in an ON state, a high-voltageis outputted at the HV_(out). Since a voltage (V_(H)+V_(THN)) is appliedto a gate of the HVN2, a voltage V_(H), which is not dropped by athreshold voltage V_(THN) of the HVN2, becomes outputted as an outputlevel of the high-voltage in the output voltage terminal HV_(out).

[0036] On the other hand, if a high signal is applied to the data lineData, it operates to the contrary and a voltage 0V becomes outputted inthe output voltage terminal HV_(out).

[0037] Thus, in this embodiment of the present invention, an inputvoltage V_(H) of a high-voltage applied can be also outputted as it iswith using a high-voltage NMOS as a pull-up element of a high-voltageoutput terminal and without dropping a voltage by a threshold voltage ofthe high-voltage element. At the same time, it is advantageous that thehigh-voltage output terminal occupies a smaller area as compared with astructure using high-voltage PMOS transistors for a full swing.

[0038] The above-mentioned high-voltage output terminal circuitsaccording to the embodiments of the present invention are used for ascan driving IC and a data driving IC as a driving IC of a plasmadisplay panel, or for a driving IC and a data driving IC as a driving ICof another flat display.

[0039]FIGS. 8a to 8 c illustrate voltage waveforms at the output voltageterminal HV_(out), and nodes 2 and 3 for comparing an output voltage inthe conventional high-voltage output terminal circuit with an outputvoltage in the high-voltage output terminal circuit according to thepresent invention.

[0040]FIGS. 8a to 8 c show results of an HSPICE simulation afterapplying 180V to V_(H) in the high-voltage output terminal circuit. FIG.8a shows an output voltage HV_(out) of the conventional high-voltageoutput terminal circuit and of the high-voltage output terminal circuitaccording to the present invention as a proposed HV driver, which isshowing that a full swing of 180V causes in the present invention, but afull swing does not occurs as the output voltage is 178V in theconventional circuit. Also, FIG. 8b shows a voltage at the node 2 of thehigh-voltage output terminal, and FIG. 8c shows a voltage at the node 3of the high-voltage output terminal, wherein, at the node 2, the voltagein the high-voltage output terminal of the present invention shows 183Vand the voltage in the conventional circuit shows 180V, while thevoltage in the high-voltage output terminal of the present inventionshows 182V at the node 3 and the voltage in the conventional circuitshows 179V at the node 3.

[0041] According to the configuration and acting of the high-voltageoutput circuits for a driving circuit of a plasma display panel and thelike in accordance with the embodiments of the present inventiondescribed above, the high-voltage output circuits comprise ahigh-voltage level shifter and a high-voltage output means including ahigh-voltage NMOS as a pull-up element, or a bootstrapping circuit,wherein the same input voltage as a predetermined output voltage and adata signal are inputted and an output voltage of a high-voltage pulsecorresponding to the data signal is outputted, and which can prevent adrop in a threshold voltage of the high-voltage element with usinghigh-voltage NMOS transistors only and therefore can reduce an area ascompared with a structure using high-voltage PMOS transistors for a fullswing.

[0042] Although the invention has been described in connection withspecific preferred embodiments, it should be understood that the presentinvention should not be unduly limited to such specific embodiments. Itwill be apparent for those skilled in the art that variousmodifications, improvements or applications are possible with respect tothe shown embodiments within the scope of the present invention.

1. A high-voltage output circuit for a driving circuit of a plasmadisplay panel and the like, which comprises a high-voltage level shifter10 and a high-voltage output means 20 including a high-voltage NMOS as apull-up element, wherein the same input voltage V_(H) as a predeterminedoutput voltage HV_(out) and a data signal are inputted and an outputvoltage HV_(out) of a high-voltage pulse corresponding to the datasignal is outputted, said high-voltage output circuit beingcharacterized by further comprising: a boosting voltage generator 30between the input voltage V_(H) and the high-voltage level shifter 10for raising the input voltage V_(H) to a higher voltage (V_(H)+V_(THN))by a threshold voltage V_(THN) of a high-voltage NMOS transistor so asto prevent a voltage drop in the output voltage HV_(out) of thehigh-voltage NMOS of the high-voltage output means
 20. 2. A high-voltageoutput circuit for a driving circuit of a plasma display panel and thelike according to claim 1, said high-voltage level shifter 10comprising: a LVPMOS1 and a LVPMOS2 transistors for constituting alatch; a HVPMOS1 and a HVPMOS2 transistors for clamping a gate voltageof, and protecting, the LVPMOS1 and the LVPMOS2 transistors; a LVNMOS1and a LVNMOS2 transistors for turning on/off the LVPMOS1 transistor andturning off/on the LVPMOS2 transistor by means of the HVPMOS1 and theHVPMOS2 transistors by becoming off and on/on and off by means of a lowsignal(0V)/a high signal of the data line, respectively; a HVNMOS1 and aHVPMOS3 transistors to become off/on and on/off by means of the lowsignal(0V)/the high signal of the data line, respectively, so as toapply the higher voltage (V_(H)+V_(THN)) to a gate of the high-voltageNMOS transistor of the high-voltage output means 20 from said HVPMOS3transistor when the data line is a low signal(0V).
 3. A high-voltageoutput circuit for a driving circuit of a plasma display panel and thelike according to claim 1 or claim 2, wherein said high-voltage outputcircuit is included by a scan driving IC and a data driving IC as adriving IC of a plasma display panel.
 4. A high-voltage output circuitfor a driving circuit of a plasma display panel and the like accordingto claim 1 or claim 2, wherein said high-voltage output circuit isincluded by a scan driving IC and a data driving IC as a driving IC of aflat display.
 5. A high-voltage output circuit for a driving circuit ofa plasma display panel and the like, which comprises a high-voltagelevel shifter 110 and a high-voltage output means 120 including ahigh-voltage NMOS transistor as a pull-up element, wherein the sameinput voltage V_(H) as a predetermined output voltage HV_(out) and adata signal are inputted and an output voltage HV_(out) of ahigh-voltage pulse corresponding to the data signal is outputted, saidhigh-voltage output circuit being characterized by further comprising: abootstrapping high-voltage level shifter 130 between the high-voltagelevel shifter 110 and the high-voltage output means 120 for raising theinput voltage V_(H) to a higher voltage (V_(H)+V_(THN)) by a thresholdvoltage V_(THN) of a high-voltage NMOS transistor so as to prevent avoltage drop in the output voltage HV_(out) of the high-voltage NMOS ofthe high-voltage output means
 120. 6. A high-voltage output circuit fora driving circuit of a plasma display panel and the like according toclaim 5, said bootstrapping high-voltage level shifter 130 comprising acharge pumping means C_(pump) having a buffer and a capacitor for thebootstrapping, thereby applying a higher voltage (V_(H)+V_(THN)) by thethreshold voltage V_(THN) than the final output voltage HV_(out) to agate part of the high-voltage NMOS transistor or the pull-up element ofthe high-voltage output means and outputting the input voltage V_(H)without dropping the threshold voltage V_(THN) on outputting thehigh-voltage.
 7. A high-voltage output circuit for a driving circuit ofa plasma display panel and the like according to claim 5 or claim 6,said high-voltage level shifter 110 comprising: a LVP1 and a LVP2transistors for constituting a latch; a HVP1 and a HVP2 transistors forclamping a gate voltage of, and protecting, the LVP1 and the LVP2transistors; a LVN1 and a LVN2 transistors for turning on/off the LVP1transistor and turning off/on the LVP2 transistor by means of the HVP1and the HVP2 transistors by becoming off and on/on and off by means of alow signal(0V)/a high signal of the data line, respectively; a HVN1 anda HVP3 transistors to become off/on and on/off by means of the lowsignal(0V)/the high signal of the data line, respectively, so as toapply a voltage (V_(H)+V_(THN)) to a gate of the high-voltage NMOStransistor of the high-voltage output means 120 from said HVP3transistor when the data line is a low signal(0V).
 8. A high-voltageoutput circuit for a driving circuit of a plasma display panel and thelike according to claim 5 or claim 6, wherein said high-voltage outputcircuit is included by a scan driving IC and a data driving IC as adriving IC of a plasma display panel and by a scan driving IC and a datadriving IC as a driving IC of a flat display.